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| ? 2008 microchip technology inc. ds21682d-page 1 24lcs22a features: ? single supply with operation down to 2.5v ? supports enhanced edid ? (e-edid ? ) 1.3 ? completely implements ddc1 ? /ddc2 ? inter- face for monitor identification, including recovery to ddc1 ? 2 kbit serial eeprom low-power cmos technology: - 1 ma active current, typical -10 a standby current, typical at 5.5v ? 2-wire serial interface bus, i 2 c ? compatible ? 100 khz (2.5v) and 400 khz (5v) compatibility ? self-timed write cycle (including auto-erase) ? hardware write-protect pin ? page write buffer for up to eight bytes ? 1,000,000 erase write cycles ? data retention >200 years ? esd protection >4000v ? 8-pin pdip and soic packages ? available temperature ranges: ? pb-free and rohs compliant description: the microchip technology inc. 24lcs22a is a 256 x 8-bit dual-mode electrically erasable prom (eeprom). this device is designed for use in applications requiring storage and serial transmission of configuration and control information. two modes of operation have been implemented: transmit-only mode (1 kbit) and bidirectional mode (2 kbit). upon power-up, the device will be in the transmit-only mode, sending a serial bit stream of the memory array from 00h to 7fh, clocked by the vclk pin. a valid high-to-low transition on the scl pin will cause the device to enter the transition mode, and look for a valid control byte on the i 2 c bus. if it detects a valid control byte from the master, it will switch into bidirectional mode, with byte selectable read/write capability of the entire 2k memory array using scl. if no control byte is received, the device will revert to the trans- mit-only mode after it receives 128 consecutive vclk pulses while the scl pin is idle. the 24lcs22a is avail- able in standard 8-pin pdip and soic packages. the 24lcs22a features a flexible write-protect pin which is enabled by writing to address 7fh (usually the checksum in vesa ? applications. package types block diagram - industrial (i) -40c to +85c pdip/soic 24lcs22a *nc *nc wp v ss 1 2 3 4 8 7 6 5 v cc vclk scl sda * pins labeled ?nc? have no internal connection hv generator eeprom array page latches ydec xdec sense amp. r/w control memory control logic i/o control logic wp sda scl vcc vss vclk 2k vesa ? e-edid ? serial eeprom
24lcs22a ds21682d-page 2 ? 2008 microchip technology inc. 1.0 electrical characteristics absolute maximum ratings (?) v cc ............................................................................................................................... ..............................................7.0v all inputs and outputs w.r.t. v ss ......................................................................................................... -0.6v to v cc +1.0v storage temperature ............................................................................................................ ...................-65 c to +150 c ambient temperature with power applied ......................................................................................... .......-40 c to +125 c esd protection on all pins ............................................................... ............................................................... ........................ 4kv table 1-1: dc characteristics ? notice: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. dc characteristics vcc = +2.5v to 5.5v industrial (i): t a = -40c to +85c param. no. sym characteristic min. max. units test conditions scl and sda pins: d1 v ih high-level input voltage 0.7 v cc ?v d2 v il low-level input voltage ? 0.3 v cc v input levels on vclk pin: d3 v ih high-level input voltage 2.0 ? v v cc 2.7v (note) d4 v il low-level input voltage ? 0.2 v cc vv cc 2.7v (note) d5 v hys hysteresis of schmitt trigger inputs .05 v cc ?v (note) d6 v ol 1 low-level output voltage ? 0.4 v i ol = 3 ma, v cc = 2.5v (note) d7 v ol 2 low-level output voltage ? 0.6 v i ol = 6 ma, v cc = 2.5v d8 i li input leakage current ? 1 av in = 0.1v to v cc d9 i lo output leakage current ? 1 av out = 0.1v to v cc d10 c in , c out pin capacitance (all inputs/outputs) ?10pfv cc = 5.0v (note) t a = 25c, f clk = 1 mhz operating current: d10 i cc w rite operating current ? 3 ma v cc = 5.5v, d11 i cc r ead operating current ? 1 ma v cc = 5.5v, scl = 400 khz d12 i ccs standby current ? ? 30 100 a a v cc = 3.0v, sda = scl = v cc v cc = 5.5v, sda = scl = v cc v clk = v ss note: this parameter is periodically sampled and not 100% tested. ? 2008 microchip technology inc. ds21682d-page 3 24lcs22a table 1-2: ac characteristics ac characteristics vcc = +2.5v to 5.5v industrial (i): t a = -40c to +85c param. no. sym parameter min max units conditions 1f clk clock frequency ? ? 100 400 khz 2.5v v cc 5.5v 4.5v v cc 5.5v 2t high clock high time 4000 600 ? ? ns 2.5v v cc 5.5v 4.5v v cc 5.5v 3t low clock low time 4700 1300 ? ? ns 2.5v v cc 5.5v 4.5v v cc 5.5v 4t r sda and scl rise time ? ? 1000 300 ns 2.5v v cc 5.5v ( note 1 ) 4.5v v cc 5.5v ( note 1 ) 5t f sda and scl fall time ? ? 300 300 ns ( note 1 ) 6t hd : sta start condition hold time 4000 600 ? ? ns 2.5v v cc 5.5v 4.5v v cc 5.5v 7t su : sta start condition setup time 4700 600 ? ? ns 2.5v v cc 5.5v 4.5v v cc 5.5v 8t hd : dat data input hold time 0 0 ? ? ns ( note 2 ) 9t su : dat data input setup time 250 100 ? ? ns 2.5v v cc 5.5v 4.5v v cc 5.5v 10 t su : sto stop condition setup time 4000 600 ? ? ns 2.5v v cc 5.5v 4.5v v cc 5.5v 11 t aa output valid from clock ( note 2 ) ? ? 3500 900 ns 2.5v v cc 5.5v 4.5v v cc 5.5v 12 t buf bus free time: time the bus must be free before a new transmission can start 4700 1300 ? ? ns 2.5v v cc 5.5v 4.5v v cc 5.5v 13 t of output fall time from v ih minimum to v il maximum ? 20+0.1c b 250 250 ns 2.5v v cc 5.5v ( note 1 ) 4.5v v cc 5.5v ( note 1 ) 14 t sp input filter spike suppression (sda and scl pins) ? ? 50 50 ns ( notes 1 and 3 ) 15 t wr write cycle time (byte or page) ? ? 10 10 ms 16 t vaa output valid from vclk ? ? 2000 1000 ns 17 t vhigh vclk high time 4000 600 ? ? ns 18 t vlow vclk low time 4700 1300 ? ? ns 19 t vhst vclk setup time 0 0 ? ? ns 20 t spvl vclk hold time 4000 600 ? ? ns 21 t vhz mode transition time ? ? 1000 500 ns 22 t vpu transmit-only power-up time 0 0 ? ? ns 23 t spv input filter spike suppression (vclk pin) ? ? 100 100 ns 24 ? endurance 1m ? cycles 25c, v cc = 5.0v, block mode ( note 4 ) note 1: not 100% tested. c b = total capacitance of one bus line in pf. 2: as a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. 3: the combined t sp and v hys specifications are due to schmitt trigger inputs which provide improved noise spike suppression. this eliminates the need for a ti specification for standard operation. 4: this parameter is not tested but established by characterization. for endurance estimates in a specific application, please con sult the total endurance? model which can be obtained from microchip?s web site at www.microchip.com. 24lcs22a ds21682d-page 4 ? 2008 microchip technology inc. 2.0 functional description the 24lcs22a is designed to comply to the ddc standard proposed by vesa (figure 3-3) with the exception that it is not access.bus? capable. it oper- ates in two modes, the transmit-only mode (1 kbit) and the bidirectional mode (2 kbit). there is a separate 2-wire protocol to support each mode, each having a separate clock input but sharing a common data line (sda). the device enters the transmit-only mode upon power-up. in this mode, the device transmits data bits on the sda pin in response to a clock signal on the vclk pin. the device will remain in this mode until a valid high-to-low transition is placed on the scl input. when a valid transition on scl is recognized, the device will switch into the bidirectional mode and look for its control byte to be sent by the master. if it detects its control byte, it will stay in the bidirectional mode. otherwise, it will revert to the transmit-only mode after it sees 128 vclk pulses. 2.1 transmit-only mode the device will power up in the transmit-only mode at address 00h. this mode supports a unidirectional 2-wire protocol for continuous transmission of the first 1 kbit of the memory array. this device requires that it be initialized prior to valid data being sent in the trans- mit-only mode ( section 2.2 ?initialization proce- dure? ). in this mode, data is transmitted on the sda pin in 8-bit bytes, with each byte followed by a ninth, null bit (figure 2-1). the clock source for the transmit- only mode is provided on the vclk pin, and a data bit is output on the rising edge on this pin. the eight bits in each byte are transmitted most significant bit first. each byte within the memory array will be output in sequence. after address 7fh in the memory array is transmitted, the internal address pointers will wrap around to the first memory location (00h) and continue. the bidirectional mode clock (scl) pin must be held high for the device to remain in the transmit-only mode. 2.2 initialization procedure after v cc has stabilized, the device will be in the trans- mit-only mode. nine clock cycles on the vclk pin must be given to the device for it to perform internal sychronization. during this period, the sda pin will be in a high-impedance state. on the rising edge of the tenth clock cycle, the device will output the first valid data bit which will be the most significant bit in address 00h. (figure 2-2). figure 2-1: transmit-only mode figure 2-2: device initialization scl sda vclk t vaa t vaa bit 1 (lsb) null bit bit 1 (msb) bit 7 t vlow t vhigh t vaa t vaa bit 8 bit 7 high-impedance for 9 clock cycles t vpu 12 891011 scl sda vclk v cc ? 2008 microchip technology inc. ds21682d-page 5 24lcs22a 3.0 bidirectional mode before the 24lcs22a can be switched into the bidirectional mode (figure 3-1), it must enter the transition mode, which is done by applying a valid high-to-low transition on the bidirectional mode clock (scl). as soon as it enters the transition mode, it looks for a control byte ?1010 000x? on the i 2 c? bus, and starts to count pulses on vclk. any high-to-low transition on the scl line will reset the count. if it sees a pulse count of 128 on vclk while the scl line is idle, it will revert back to the transmit-only mode, and transmit its contents starting with the most significant bit in address 00h. however, if it detects the control byte on the i 2 c bus (figure 3-2), it will switch to the bidirectional mode. once the device has made the transition to the bidirectional mode, the only way to switch the device back to the transmit-only mode is to remove power from the device. the mode transition process is shown in detail in figure 3-3. once the device has switched into the bidirectional mode, the vclk input is disregarded, with the exception that a logic high level is required to enable write capability. in bidirectional mode the user has access to the entire 2k array, whereas in the transmit- only mode, the user can only access the first 1k. this mode supports a two-wire bidirectional data transmission protocol (i 2 c). in this protocol, a device that sends data on the bus is defined to be the transmitter, and a device that receives data from the bus is defined to be the receiver. the bus must be controlled by a master device that generates the bidirectional mode clock (scl), controls access to the bus and generates the start and stop conditions, while the 24lcs22a acts as the slave. both master and slave can operate as transmitter or receiver, but the master device determines which mode is activated. in the bidirectional mode, the 24lcs22a only responds to commands for device ?1010 000x? . figure 3-1: mode transition with recovery to transmit-only mode figure 3-2: successful mode transition to bidirectional mode t vhz scl sda vclk transmit-only mode bidirectional recovery to transmit-only mode bit8 (msb of data in 00h) vclk count = 1 2 3 4 127 128 transition mode with possibility to return to transmit-only mode bidirectional permanently scl sda vclk count = 1 2 n 0 vclk transmit-only mode s 1010 0 000 ack n < 128 24lcs22a ds21682d-page 6 ? 2008 microchip technology inc. figure 3-3: display operation per ddc standard proposed by vesa ? communication is idle is vsync present? no send edid? continuously using vsync as clock high-to-low transition on scl? no ye s yes stop sending edid. switch to ddc2? mode. display has transition state ? optional set vsync counter = 0 change on vclk lines? scl, sda or no yes high-low transition on scl ? reset vsync counter = 0 no yes valid received? ddc2 address no no vclk cycle? ye s increment vclk counter yes switch back to ddc1? mode. ddc2 communication idle. display waiting for address byte. ddc2b address received? ye s receive ddc2b command respond to ddc2b command is display access.bus? yes valid access.bus address? no yes see access.bus specification to determine correct procedure. yes no ye s no no no the 24lcs22a was designed to display power-on or ddc circuit powered from +5 volts or start timer reset counter or timer (if appropriate) counter=128 or timer expired? high-to-low transition on scl? no ye s comply to the portion of flowchart inside dash box note 1: the base flowchart is copyright ? 1993, 1994, 1995 video electronic standard association (vesa) from vesa?s display data channel (ddc) standard proposal ver. 2p rev. 0, used by permission of vesa. 2: the dash box and text ?the 24lcs22a and... inside dash box.? are added by microchip technology inc. 3: vsync signal is normally used to derive a signal for vclk pin on the 24lcs22a. capable? ? 2008 microchip technology inc. ds21682d-page 7 24lcs22a 3.1 bidirectional mode bus characteristics the following bus protocol has been defined: ? data transfer may be initiated only when the bus is not busy ? during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line while the clock line is high will be interpreted as a start or stop condition accordingly, the following bus conditions have been defined (figure 3-4). 3.1.1 bus not busy (a) both data and clock lines remain high. 3.1.2 start data transfer (b) a high-to-low transition of the sda line while the clock (scl) is high determines a start condition. all commands must be preceded by a start condition. 3.1.3 stop data transfer (c) a low-to-high transition of the sda line while the clock (scl) is high determines a stop condition. all operations must be ended with a stop condition. 3.1.4 data valid (d) the state of the data line represents valid data when, after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line must be changed during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start condition and terminated with a stop condition. the number of the data bytes transferred between the start and stop conditions is determined by the master device and is theoretically unlimited, although only the last eight will be stored when doing a write operation. when an overwrite does occur it will replace data in a first-in first- out (fifo) fashion. 3.1.5 acknowledge each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. the master device must generate an extra clock pulse which is associated with this acknowledge bit. the device that acknowledges has to pull down the sda line during the acknowledge clock pulse in such a way that the sda line is stable low during the high period of the acknowledge related clock pulse. of course, setup and hold times must be taken into account. a master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. in this case, the slave must leave the data line high to enable the master to generate the stop condition. figure 3-4: data transfer sequence on the serial bus note: once switched into bidirectional mode, the 24lcs22a will remain in that mode until power is removed. removing power is the only way to reset the 24lcs22a into the transmit-only mode. note: the 24lcs22a does not generate any acknowledge bits if an internal programming cycle is in progress. (a) (b) (d) (d) (a) (c) start condition address or acknowledge valid data allowed to change stop condition scl sda 24lcs22a ds21682d-page 8 ? 2008 microchip technology inc. figure 3-5: bus timing start/stop figure 3-6: bus timing data 3.1.6 slave address after generating a start condition, the bus master transmits the slave address consisting of a 7-bit device code ( 1010000 ) for the 24lcs22a. the eighth bit of slave address determines whether the master device wants to read or write to the 24lcs22a (figure 3-7). the 24lcs22a monitors the bus for its corresponding slave address continuously. it generates an acknowledge bit if the slave address was true and it is not in a programming mode. figure 3-7: control byte allocation scl sda start stop v hys t su : sto t hd : sta t su : sta scl sda in sda out t su : sta t sp t aa t f t low t high t hd : sta t hd : dat t su : dat t su : sto t buf t aa t r operation slave address r/w read 1010000 1 write 1010000 0 r/w a 1 0100 00 read/write start slave address ? 2008 microchip technology inc. ds21682d-page 9 24lcs22a 4.0 write operation 4.1 byte write following the start signal from the master, the slave address (four bits), three zero bits ( 000 ) and the r/w bit which is a logic low are placed onto the bus by the master transmitter. this indicates to the addressed slave receiver that a byte with a word address will follow after it has generated an acknowledge bit during the ninth clock cycle. therefore, the next byte transmitted by the master is the word address and will be written into the address pointer of the 24lcs22a. after receiving another acknowledge signal from the 24lcs22a the master device will transmit the data word to be written into the addressed memory location. the 24lcs22a acknowledges again and the master generates a stop condition. this initiates the internal write cycle, and during this time the 24lcs22a will not generate acknowledge signals (figure 4-1). it is required that vclk be held at a logic high level during command and data transfer in order to program the device. this applies to both byte write and page write operation. note, however, that the vclk is ignored during the self-timed program operation. changing vclk from high-to-low during the self-timed program operation will not halt programming of the device. 4.2 page write the write control byte, word address and the first data byte are transmitted to the 24lcs22a in the same way as in a byte write. but instead of generating a stop condition the master transmits up to eight data bytes to the 24lcs22a which are temporarily stored in the on- chip page buffer and will be written into the memory after the master has transmitted a stop condition. after the receipt of each word, the three lower order address pointer bits are internally incremented by one. the higher order five bits of the word address remains constant. if the master should transmit more than eight words prior to generating the stop condition, the address counter will roll over and the previously received data will be overwritten. as with the byte write operation, once the stop condition is received an internal write cycle will begin (figure 5-2). it is required that vclk be held at a logic high level during command and data transfer in order to program the device. this applies to both byte write and page write operation. note, however, that the vclk is ignored during the self-timed program operation. changing vclk from high-to-low during the self-timed program operation will not halt programming of the device. note: page write operations are limited to writing bytes within a single physical page, regardless of the number of bytes actually being written. physical page boundaries start at addresses that are integer multiples of the page buffer size (or ?page size?) and end at addresses that are integer multiples of [page size ? 1]. if a page write command attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page as might be expected. it is therefore necessary for the application software to prevent page write operations that would attempt to cross a page boundary. 24lcs22a ds21682d-page 10 ? 2008 microchip technology inc. figure 4-1: byte write figure 4-2: vclk write enable timing bus activity master sda line bus activity control byte word address data s t o p s t a r t a c k s p a c k a c k vclk scl sda in vclk t hd : sta t su : sto t vhst t spvl ? 2008 microchip technology inc. ds21682d-page 11 24lcs22a 5.0 acknowledge polling since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). once the stop condition for a write command has been issued from the master, the device initiates the internally timed write cycle. ack polling can be initiated immediately. this involves the master sending a start condition followed by the control byte for a write command (r/w = 0 ). if the device is still busy with the write cycle, then no ack will be returned. if the cycle is complete, then the device will return the ack and the master can then proceed with the next read or write command. see figure 5-1 for the flow diagram. figure 5-1: acknowledge polling flow figure 5-2: page write did device acknowledge (ack = 0 )? send write command send stop condition to initiate write cycle send start send control byte with r/w = 0 next operation no yes sda line control byte word address s t o p s t a r t a c k a c k a c k a c k a c k data n + 1 data n + 7 data (n) p s vclk bus activity master bus activity 24lcs22a ds21682d-page 12 ? 2008 microchip technology inc. 6.0 write protection when using the 24lcs22a in the bidirectional mode, the vclk pin can be used as a write-protect control pin. setting vclk high allows normal write operations, while setting vclk low prevents writing to any location in the array. connecting the vclk pin to v ss would allow the 24lcs22a to operate as a serial rom, although this configuration would prevent using the device in the transmit-only mode. additionally, pin 3 performs a flexible write-protect function. the 24lcs22a contains a write protection control fuse whose factory default state is cleared. writing any data to address 7fh (normally the checksum in ddc applications) sets the fuse which enables the wp pin. until this fuse is set, the 24lcs22a is always write enabled (if vclk = 1 ). after the fuse is set, the write capability of the 24lcs22a is determined by both vclk and wp pins (table 6-1). table 6-1: write-protect truth table 7.0 read operation read operations are initiated in the same way as write operations with the exception that the r/w bit of the slave address is set to one. there are three basic types of read operations: current address read, random read and sequential read. 7.1 current address read the 24lcs22a contains an address counter that maintains the address of the last word accessed, internally incremented by one. therefore, if the previous access (either a read or write operation) was to address n, the next current address read operation would access data from address n + 1. upon receipt of the slave address with r/w bit set to one, the 24lcs22a issues an acknowledge and transmits the eight bit data word. the master will not acknowledge the transfer, but does generate a stop condition and the 24lcs22a discontinues transmission (figure 7-1). figure 7-1: current address read 7.2 random read random read operations allow the master to access any memory location in a random manner. to perform this type of read operation, first the word address must be set. this is done by sending the word address to the 24lcs22a as part of a write operation. after the word address is sent, the master generates a start condition following the acknowledge. this terminates the write operation, but not before the internal address pointer is set. then the master issues the control byte again but with the r/w bit set to a one. the 24lcs22a will then issue an acknowledge and transmits the 8-bit data word. the master will not acknowledge the transfer, but does generate a stop condition and the 24lcs22a discontinues transmission (figure 7-2). vclk wp address 7fh written mode for 00h-7fh 0 xx read-only 1 x no r/w 1 1/open x r/w 1 0 yes read-only control a c k sp byte data n bus activity sda line bus activity a c k n o master 101 0000 1 s t o p s t a r t ? 2008 microchip technology inc. ds21682d-page 13 24lcs22a figure 7-2: random read figure 7-3: sequential read 7.3 sequential read sequential reads are initiated in the same way as a random read except that after the 24lcs22a transmits the first data byte, the master issues an acknowledge as opposed to a stop condition in a random read. this directs the 24lcs22a to transmit the next sequentially addressed 8-bit word (figure 7-3). to provide sequential reads the 24lcs22a contains an internal address pointer which is incremented by one at the completion of each operation. this address pointer allows the entire memory contents to be serially read during one operation. 7.4 noise protection the 24lcs22a employs a v cc threshold detector circuit which disables the internal erase/write logic if the v cc is below 1.5 volts at nominal conditions. the sda, scl and vclk inputs have schmitt trigger and filter circuits which suppress noise spikes to assure proper device operation even on a noisy bus. bus activity master sda line bus activity control byte word address data n a c k s t a r t n o s t a r control byte a c k a c k ss t p s t o p 10100000 0 0 0 0 01 1 1 a c k a c k p bus activity master sda line bus activity control byte data n data n + 1 data n + 2 data n + x a c k a c k a c k n o a c k s t o p 24lcs22a ds21682d-page 14 ? 2008 microchip technology inc. 8.0 pin descriptions the descriptions of the pins are listed in table 8-1. table 8-1: pin function table 8.1 write-protect (wp ) this pin is used for flexible write protection of the 24lcs22a. when memory location 7fh is written with any data, this pin is enabled and determines the write capability of the 24lcs22a (table 6-1). 8.2 serial address/data input/output (sda) this pin is used to transfer addresses and data into and out of the device, when the device is in the bidirectional mode. in the transmit-only mode, which only allows data to be read from the device, data is also transferred on the sda pin. this pin is an open drain terminal, therefore the sda bus requires a pull-up resistor to v cc (typical 10 k for 100 khz, 2 k for 400 khz). for normal data transfer in the bidirectional mode, sda is allowed to change only during scl low. changes during scl high are reserved for indicating the start and stop conditions. 8.3 serial clock (scl) this pin is the clock input for the bidirectional mode, and is used to synchronize data transfer to and from the device. it is also used as the signaling input to switch the device from the transmit-only mode to the bidirectional mode. it must remain high for the chip to continue operation in the transmit-only mode. 8.4 serial clock (vclk) this pin is the clock input for the transmit-only mode (ddc1). in the transmit-only mode, each bit is clocked out on the rising edge of this signal. in the bidirectional mode, a high logic level is required on this pin to enable write capability. name function wp write-protect (active low) v ss ground sda serial address/data i/o scl serial clock (bidirectional mode) vclk serial clock (transmit-only mode) v cc +2.5v to 5.5v power supply nc no internal connection ? 2008 microchip technology inc. ds21682d-page 15 24lcs22a 9.0 packaging information 9.1 package marking information xxxxxxxx xxxxxnnn yyww 8-lead pdip (300 mil) example: 24lcs22a i/pnnn 0145 8-lead soic (3.90 mm) example: * standard marking consists of microchip part number, year code, week code, traceability code (facility code, mask rev#, and assembly code). xxxxxxxx xxxxyyww nnn 24lcs22a i/sn0145 nnn legend: xx...x part number or part number code t temperature (i, e) y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code (2 characters for small packages) pb-free jedec designator for matte tin (sn) note : for very small packages with no room for the pb-free jedec designator , the marking will only appear on the outer carton or reel label. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e 24lcs22a ds21682d-page 16 ? 2008 microchip technology inc. !" #$% &" ' ()"&'"!&) &#*& & & # +% &, & !& - '! ! #. # &"#' #% ! & "! ! #% ! & "! !! &$# / !# '! #& .0 1,21 !'! & $ & "! **& "&& ! 3 & ' !&" & 4 # *!( !!& 4 % & &# & && 255***' '5 4 6&! 7,8. '! 9'&! 7 7: ; 7"') % ! 7 < & 1, & & = = ## 4 4!! - 1 !& & = = "# & "# >#& . - - ## 4 >#& . < : 9& -< -? & & 9 - 9 # 4!! < 6 9 #>#& ) ? 9 * 9 #>#& ) < : * + 1 = = - n e1 note 1 d 12 3 a a1 a2 l b1 b e e eb c * , <1 ? 2008 microchip technology inc. ds21682d-page 17 24lcs22a ! ""#$%& !' !" #$% &" ' ()"&'"!&) &#*& & & # +% &, & !& - '! ! #. # &"#' #% ! & "! ! #% ! & "! !! &$# '' !# '! #& .0 1,2 1 !'! & $ & "! **& "&& ! .32 % '! ("!" *& "&& (% % ' & " !! 3 & ' !&" & 4 # *!( !!& 4 % & &# & && 255***' '5 4 6&! 99. . '! 9'&! 7 7: ; 7"') % ! 7 < & 1, : 8 & = = ## 4 4!! = = & # %% + = : >#& . ?1, ## 4 >#& . -1, : 9& 1, , '% @ & a = 3 &9& 9 = 3 & & 9 .3 3 & b = #& ) - = # %& b = b # %&1 && ' b = b d n e e e1 note 1 12 3 b a a1 a2 l l1 c h h * , 1 24lcs22a ds21682d-page 18 ? 2008 microchip technology inc. ! ""#$%& !' 3 & ' !&" & 4 # *!( !!& 4 % & &# & && 255***' '5 4 ? 2008 microchip technology inc. ds21682d-page 19 24lcs22a appendix a: revision history revision b corrections to section 1.0, electrical characteristics. revision c revised section 8.1. added new package legend. revision d (07/2008) revised features (added pb-free); replaced package drawings (rev. ap); revised product id system. 24lcs22a ds21682d-page 20 ? 2008 microchip technology inc. notes: ? 2008 microchip technology inc. ds21682d-page 21 24lcs22a the microchip web site microchip provides online support via our www site at www.microchip.com. this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site contains the following information: ? product support ? data sheets and errata, application notes and sample programs, design resources, user?s guides and hardware support documents, latest software releases and archived software ? general technical support ? frequently asked questions (faq), technical support requests, online discussion groups, microchip consultant program member listing ? business of microchip ? product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of microchip sales offices, distributors and factory representatives customer change notification service microchip?s customer notification service helps keep customers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com, click on customer change notification and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: ? distributor or representative ? local sales office ? field application engineer (fae) ? technical support ? development systems information line customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this document. technical support is available through the web site at: http://support.microchip.com 24lcs22a ds21682d-page 22 ? 2008 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip prod- uct. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outline to provide us with your comments about this document. to : technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds21682d 24lcs22a 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you think would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document? ? 2008 microchip technology inc. ds21682d-page 23 24lcs22a product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . part no. x /xx package temperature range device device: 24lcs22a: 2k vesa e-edid serial eeprom 24lcs22at: 2k vesa e-edid serial eeprom (tape and reel) temperature range: i = -40c to +85c package: p = plastic dip (300 mil body), 8-lead sn = plastic soic (3.90 mm body), 8-lead examples: a) 24lcs22a-i/p: industrial temperature, pdip package. b) 24lcs22a-i/sn: industrial temperature, soic package. c) 24lcs22at-i/sn:tape and reel, industrial temperature, soic package. 24lcs22a ds21682d-page 24 ? 2008 microchip technology inc. notes: ? 2008 microchip technology inc. ds21682d-page 25 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, accuron, dspic, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, pro mate, rfpic and smartshunt are registered trademarks of microchip tec hnology incorporated in the u.s.a. and other countries. filterlab, linear active thermistor, mxdev, mxlab, seeval, smartsensor and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, appl ication maestro, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, in-circuit serial programming, icsp, icepic, mindi, miwi, mpasm, mplab certified logo, mplib, mplink, mtouch, pickit, picdem, picdem.net, pictail, pic 32 logo, powercal, powerinfo, powermate, powertool, real ice, rflab, select mode, total endurance, uni/o, wiperlock and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2008, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. ds21682d-page 26 ? 2008 microchip technology inc. americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: http://support.microchip.com web address: www.microchip.com atlanta duluth, ga tel: 678-957-9614 fax: 678-957-1455 boston westborough, ma tel: 774-760-0087 fax: 774-760-0088 chicago itasca, il tel: 630-285-0071 fax: 630-285-0075 dallas addison, tx tel: 972-818-7423 fax: 972-818-2924 detroit farmington hills, mi tel: 248-538-2250 fax: 248-538-2260 kokomo kokomo, in tel: 765-864-8360 fax: 765-864-8387 los angeles mission viejo, ca tel: 949-462-9523 fax: 949-462-9608 santa clara santa clara, ca tel: 408-961-6444 fax: 408-961-6445 toronto mississauga, ontario, canada tel: 905-673-0699 fax: 905-673-6509 asia/pacific asia pacific office suites 3707-14, 37th floor tower 6, the gateway harbour city, kowloon hong kong tel: 852-2401-1200 fax: 852-2401-3431 australia - sydney tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing tel: 86-10-8528-2100 fax: 86-10-8528-2104 china - chengdu tel: 86-28-8665-5511 fax: 86-28-8665-7889 china - hong kong sar tel: 852-2401-1200 fax: 852-2401-3431 china - nanjing tel: 86-25-8473-2460 fax: 86-25-8473-2470 china - qingdao tel: 86-532-8502-7355 fax: 86-532-8502-7205 china - shanghai tel: 86-21-5407-5533 fax: 86-21-5407-5066 china - shenyang tel: 86-24-2334-2829 fax: 86-24-2334-2393 china - shenzhen tel: 86-755-8203-2660 fax: 86-755-8203-1760 china - wuhan tel: 86-27-5980-5300 fax: 86-27-5980-5118 china - xiamen tel: 86-592-2388138 fax: 86-592-2388130 china - xian tel: 86-29-8833-7252 fax: 86-29-8833-7256 china - zhuhai tel: 86-756-3210040 fax: 86-756-3210049 asia/pacific india - bangalore tel: 91-80-4182-8400 fax: 91-80-4182-8422 india - new delhi tel: 91-11-4160-8631 fax: 91-11-4160-8632 india - pune tel: 91-20-2566-1512 fax: 91-20-2566-1513 japan - yokohama tel: 81-45-471- 6166 fax: 81-45-471-6122 korea - daegu tel: 82-53-744-4301 fax: 82-53-744-4302 korea - seoul tel: 82-2-554-7200 fax: 82-2-558-5932 or 82-2-558-5934 malaysia - kuala lumpur tel: 60-3-6201-9857 fax: 60-3-6201-9859 malaysia - penang tel: 60-4-227-8870 fax: 60-4-227-4068 philippines - manila tel: 63-2-634-9065 fax: 63-2-634-9069 singapore tel: 65-6334-8870 fax: 65-6334-8850 taiwan - hsin chu tel: 886-3-572-9526 fax: 886-3-572-6459 taiwan - kaohsiung tel: 886-7-536-4818 fax: 886-7-536-4803 taiwan - taipei tel: 886-2-2500-6610 fax: 886-2-2508-0102 thailand - bangkok tel: 66-2-694-1351 fax: 66-2-694-1350 europe austria - wels tel: 43-7242-2244-39 fax: 43-7242-2244-393 denmark - copenhagen tel: 45-4450-2828 fax: 45-4485-2829 france - paris tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany - munich tel: 49-89-627-144-0 fax: 49-89-627-144-44 italy - milan tel: 39-0331-742611 fax: 39-0331-466781 netherlands - drunen tel: 31-416-690399 fax: 31-416-690340 spain - madrid tel: 34-91-708-08-90 fax: 34-91-708-08-91 uk - wokingham tel: 44-118-921-5869 fax: 44-118-921-5820 w orldwide s ales and s ervice 01/02/08 |
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